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ADE7816
Interrupt Enable and Interrupt Status Registers
Table 30. STATUS0 Register (Address 0xE502) and MASK0 Register (Address 0xE50A)
Data Sheet
Bits
[31:18]
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
Reserved
DREADY
Reserved
Reserved
Reserved
Reserved
REVRP3
REVRP2
REVRP1
Reserved
REVAP3
REVAP2
REVAP1
LENERGY
Reserved
REHF2
REHF1
AEHF2
AEHF1
Default Value
0 0000 0000 0000
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
These bits should be ignored.
New waveform data is ready.
This bit should be ignored.
This bit should be ignored.
This bit should be ignored.
This bit should be ignored.
The sign of the reactive power has changed (C or F channel).
The sign of the reactive power has changed (B or E channel).
The sign of the reactive power has changed (A or D channel).
This bit should be ignored.
The sign of the active power has changed (C or F channel).
The sign of the active power has changed (B or E channel).
The sign of the active power has changed (A or D channel).
The end of a line cycle accumulation period.
This bit should be ignored.
The active energy register is half full (D, E, or F channel).
The reactive energy register is half full (A, B, or C channel).
The active energy register is half full (D, E, or F channel)
The active energy register is half full (A, B, or C channel).
Table 31. STATUS1 Register (Address 0xE503) and MASK1 Register (Address 0xE50B)
Bits
[31:25]
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
Reserved
PKV
PKI
Reserved
Reserved
Reserved
Reserved
OV
OI
Sag
RSTDONE
ZXI3
ZXI2
ZXI1
Reserved
Reserved
ZXV
ZXTOI3
ZXTOI2
ZXTOI1
Reserved
Reserved
ZXTOV
Reserved
NLOAD2
NLOAD1
Default Value
0x0000000
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
These bits should be ignored.
The end of the voltage channel peak detection period.
The end of the current channel peak detection period.
This bit should be ignored.
This bit should be ignored.
This bit should be ignored.
This bit should be ignored.
An overvoltage event has occurred.
An overcurrent event has occurred.
A sag event has occurred.
The end of a software or hardware reset.
C or F current channel zero crossing.
B or E current channel zero crossing.
A or D current channel zero crossing.
This bit should be ignored.
This bit should be ignored.
Voltage channel zero crossing.
A zero crossing on the C or F current channel is missing.
A zero crossing on the B or E current channel is missing.
A zero crossing on the A or D current channel is missing.
This bit should be ignored.
This bit should be ignored.
A zero crossing on the voltage channel is missing.
This bit should be ignored.
Active and reactive no load condition on the D, E, or F current channel.
Active and reactive no load condition on the A, B, or C current channel.
Rev. A | Page 44 of 48
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